Taped lead frames and methods of making and using the same in semiconductor packaging

ABSTRACT

The invention provides a taped lead frame for use in manufacturing electronic packages. The taped lead frame is composed of a tape and a lead frame formed from a plurality of individual metal features attached to the tape and arranged in a footprint pattern. The method of making the invention enables the thickness of conventional frames to shrink significantly to result in thinner packages for improved heat dissipation and shorter geometries for improved electrical performance. A plurality of such lead frames are arranged in an array on a sheet of tape and each lead frame is separated from surrounding lead frames by street regions on the tape such that no metal feature extends into a street region. Integrated circuit chips are attached and electrically connected to the lead frames and an encapsulant is applied, cured and dried over the lead frames and the street regions. Thereafter, the tape is removed and the lead frames are singulated by cutting through the encapsulant in the street regions to form individual packages. Singulation occurs in the street regions and does not cut into any metal feature forming the lead frame.

FIELD OF THE INVENTION

The present invention generally concerns lead frames and the use thereofin the manufacture of packages containing electronic components. Inparticular, the invention concerns a taped lead frame and a method formaking and using the same in creating semiconductor electronic packages.

BACKGROUND OF THE INVENTION

Lead frames are typically made by etching or stamping a metal film tospecific shapes and dimensions. Finely configured lead frames oftenresemble very delicate embroidery, or stencil-like metal structures.Such conventional lead frames are used in the industry to create avariety of chip packages, including wire bonded and flip-chip packages.

Conventional lead frames lack structural rigidity. The finger-likeportions of lead frames are quite flimsy and difficult to hold inposition during processing. This leads to handling flaws, damage anddistortion during assembly processing.

In automated processes for making chip size packages, manufacturerstypically form a plurality of interconnected lead frames in a blockmatrix, attach and electrically connect chips to each lead frame in theblock, encapsulate the chip/lead frames, back etch the metal between thecontacts of each lead frame and then saw singulate each chip/lead frameto form individual packages. In conventional processes, however, thelead frames in the block are interconnected to one another until thesingulation step. During the process of singulating, the thickness ofthe saw blade cuts not only through the encapsulant plastic, but alsothrough the metal connections that hold the lead frames together in theblock. The force and vibration of the saw blade places undue stress onthe attachment and electrical connection between the chips and the leadframes. This can lead to structural defects, such as delamination at themetal-plastic interfaces. The present invention overcomes theseproblems.

SUMMARY OF THE INVENTION

The present invention provides a taped lead frame for use in electronicpackaging. The invention comprises etched metal features attached to adisposable tape or carrier that forms lead frame outlines in a footprintpattern. The tape or carrier may hold the metal features representingfinal form of a lead frame outline by lamination, adhesive or othersuitable method. The metal features of the lead frame provide supportand electrical connection to an integrated circuit chip. In the leadframe of the invention, each metal feature is electrically isolated fromthe other metal features in the pattern in the final form used in anindividual component or package. This invention also provides themethods of making the metal features of the lead frame on a tape orcarrier. The methods include attaching a tape or a film or carrier to ametal film or layer that forms the lead frame features for individualpackages, or, patterning a metal film to leave the required set ofisolated metal features to form a metal lead frame. Alternatively,screen printing thick metal film of even thickness onto a disposabletape, film, including glass film, or other carrier equivalents isconsidered to achieve the same formation.

The invention also concerns a method of forming an electronic packageusing a lead frame according to the invention. The method comprisesproviding a lead frame according to the invention and attaching andelectrically connecting an integrated circuit chip to the metal featuresof the lead frame. An encapsulant is then applied over the lead frame onthe tape and cured. The tape is removed and the encapsulated embodimentwith lead frame metal features securely embedded is singulated withouttouching any of the isolated metal features by design to form anelectronic package.

In a preferred embodiment, a plurality of taped lead frames according tothe invention is formed in an array for mass producing electronicpackages. In this embodiment the plurality of individual metal leadframes are attached to a sheet of the tape. Each lead frame is separatedfrom adjacent lead frames by street regions on the tape. The individualmetal features arranged in a footprint pattern forming each lead frameare electrically isolated from one another and no metal feature extendsinto a street region.

A plurality of electronic packages may be formed using the array oftaped lead frames. In this method, a plurality of integrated circuitchips are attached and electrically connected to each lead frame on thearray. Thereafter, an encapsulant is applied over the lead frames andthe street regions on the tape. In one embodiment, the encapsulatingstep includes applying the encapsulant material over the lead frame in acontrolled manner to flow around the metal features and up to the tapesurface without creating any mold flash.

Once the encapsulant is cured and dried, the tape is removed. Becausethe lead frames are electrically isolated from one another, “strip”testing may be performed at this stage, prior to singulation. The arrayis then singulated through the encapsulant in the street regions to formindividual electronic packages. Singulating can be accomplished bysawing, laser cutting, water jet cutting or a combination thereof.

The invention further includes a number of optional features. Forexample, a wire-bondable and solderable composition may be pre-plated oneither or both a first and second surface of each metal feature. Thewire-bondable and solderable composition may be Ni—Pd—Au-strike.

The metal features may have a thickness of about 1-4 mils or may be lessthan 1 mil. The tape is made of a disposable and low-cost plasticmaterial, for example, POLYIMIDE, MYLAR, KAPTON, or Fr-4 oralternatively an equivalent carrier that can be removed or disposed likeglass-film or shiny plastic film or similar. The tape or alternativecarrier may be removed by peeling, dissolving or back patterning. Inaddition, a stiffener may be incorporated below the lower surface of thetape to provide additional support and rigidity during processing. Wherea stiffener is used, it is removed prior to removing the tape during theprocess.

The metal features may be constructed and arranged in a variety offootprint patterns to accommodate the particular package beingmanufactured. For example, the metal features may be constructed forwire-bonding processing to include a die pad for supporting anintegrated circuit chip and lead contacts for electrically connectingthe lead frame to the chip. Alternatively, the metal features may beconstructed for flip-chip or land grid array processing to provide leadcontacts for both supporting an integrated circuit chip and forelectrically connecting the lead frame to the chip.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 a is top view of a taped lead frame having a plurality of chipsites, according to the present invention.

FIG. 1 b is a top view of a taped lead frame chip site showing patternedfeatures, including a chip pad and contacts surrounding the chip pad,according to the present invention.

FIG. 1 c is a cross-sectional view of the chip site taken along linesC-C in FIG. 1 b.

FIG. 1 d is a bottom view of an integrated circuit chip showing wirebonding pads.

FIG. 1 e is a top view of the placement of the chip of FIG. 1 d onto thechip pad of FIG. 1 b, according to the present invention.

FIG. 1 f is a cross-sectional view taken along lines F-F of FIG. 1 eshowing the back-bonding of the chip of FIG. 1 d onto the chip pad,according to the present invention.

FIG. 1 g is a cross-sectional view showing the wire bonding of the chippads to the electrical contacts of the taped lead frame, according tothe present invention.

FIG. 1 h is a cross-sectional view showing the encapsulation of severaltaped lead frames, including the chips and the wire bonds, to form ablock, according to the present invention.

FIG. 1 i is a cross-sectional view showing the removal of the tape andthe stiffener from the block of lead frames of FIG. 1 h, according tothe present invention.

FIG. 1 j is a cross-sectional view showing the singulation of the blockof FIG. 1 i where the saw does not encounter any metal portions of thetaped lead frame in the streets, according to the present invention.

FIG. 1 k shows a singulated taped lead frame package, according to thepresent invention.

FIG. 1 l is a top view of an array, or block, of taped lead frame chipsites, according to the present invention.

FIG. 1 m is a portion of FIG. 1 l, showing a better view of a pluralityof chip sites, according to the present invention.

FIG. 1 n is a further portion of FIG. 1 m, showing a detailed top viewof a chip site, according to the present invention.

FIG. 1 o is a flow chart showing the forming of a taped lead framepackage, according to the present invention.

FIG. 2 a is top view of a taped lead frame having a plurality of chipsites to accommodate flip-chips, according to the present invention.

FIG. 2 b is a top view of a taped lead frame chip site showing patternedfeatures, including contacts to accept a flip-chip, according to thepresent invention.

FIG. 2 c is a cross-sectional view taken along lines C-C of the chipsite of FIG. 2 b, where the tape and the optional stiffener are alsoshown, according to the present invention.

FIG. 2 d is a bottom view of an integrated circuit chip with solderbumps, according to the present invention.

FIG. 2 e is a top view of the flip-chip placement of the chip of FIG. 2d onto the electrical contacts of the taped lead frame, according to thepresent invention.

FIG. 2 f is a cross-sectional view taken along lines F-F of FIG. 2 eshowing the start of the solder flow process of the bumps, according tothe present invention.

FIG. 2 g is a cross-sectional view showing the partial collapse of thesolder bumps of FIG. 2 f after the solder flow process for theflip-chip, according to the present invention.

FIG. 2 h is a cross-sectional view showing the encapsulation of severaltaped lead frames, including the chips and the contacts, according tothe present invention.

FIG. 2 i is a cross-sectional view showing the removal of the tape andthe stiffener from the block of lead frames of FIG. 2 h, according tothe present invention.

FIG. 2 j is a cross-sectional view showing the singulation of the blockof FIG. 2 i where the saw does not encounter any metal portions of thetaped lead frame in the streets, according to the present invention.

FIG. 2 k shows a singulated taped lead frame package with a flip-chip,according to the present invention.

FIG. 2 l is a cross-sectional view of a flip chip package showing thelips formed under the contacts, according to the present invention.

FIG. 2 m is a cross-sectional view of a thermally enhanced flip chippackage, according to the present invention.

FIG. 2 n is a cross-sectional view of a near-chip size flip chippackage, according to the present invention.

FIG. 2 o is a top view of an array, or block, of taped lead frame chipsites, according to the present invention.

FIG. 2 p is a portion of FIG. 2 o, showing a better view of a pluralityof chip sites, according to the present invention.

FIG. 2 q is a further portion of FIG. 2 m, showing a detailed top viewof a chip site for a flip-chip, according to the present invention.

FIG. 2 r is a flow chart showing the forming of a flip chip package,according to the present invention.

FIG. 3 a is top view of a taped lead frame having a plurality of chipsites to accommodate land grid array flip-chips, according to thepresent invention.

FIG. 3 b is a top view of a taped lead frame chip site showing patternedcontact features, according to the present invention.

FIG. 3 c is a cross-sectional view taken along lines C-C of FIG. 3 b,where the tape and the optional stiffener are also shown, according tothe present invention.

FIG. 3 d is a bottom view of an integrated circuit chip with land gridarray solder bumps, according to the present invention.

FIG. 3 e is a cross-sectional view showing the placement of twoflip-chips of FIG. 3 d on two chip sites at the start of the solder flowprocess for the land grid array bumps, according to the presentinvention.

FIG. 3 f shows the partial collapse of the solder bumps of FIG. 3 eafter the solder flow process and the encapsulation of the leads,including the flip-chips, into a block of a molding material, accordingto the present invention.

FIG. 3 g is a cross-sectional view showing the removal of the tape andthe stiffener from the block of lead frames of FIG. 3 f, according tothe present invention.

FIG. 3 h is a cross-sectional view showing the singulation of the blockof FIG. 3 g where the saw does not encounter any metal portions of thelead frame in the streets, according to the present invention.

FIG. 3 i shows a cross-sectional view of a singulated taped lead framepackage with a land grid array flip-chip (TLGA), according to thepresent invention.

FIG. 3 j is a bottom view of the land grid array package of FIG. 3 i,according to the present invention.

FIG. 3 k shows a cross-sectional view as well as a bottom view of a TLGApackage having 256 lands, according to the present invention.

FIG. 3 l shows a cross-sectional view as well as a bottom view of a TLGApackage having 144 lands, according to the present invention.

FIG. 3 m shows a cross-sectional as well as a bottom view of a TLGApackage having 36 lands, according to the present invention.

FIG. 3 n is a top view of an array, or block, of taped lead frame chipsites to accommodate land grid array flip-chips, according to thepresent invention.

FIG. 3 o is a portion of FIG. 3 n, showing a better view of a pluralityof chip sites, according to the present invention.

FIG. 3 p is a further portion of FIG. 3 o, showing a detailed top viewof a chip site for a land grid array flip-chip, according to the presentinvention.

FIG. 3 q is a flow chart showing the forming of a land grid arraypackage, according to the present invention.

DETAILED DESCRIPTION

FIGS. 1 a-1 o show the forming of an array of taped lead frames for awire-bonded chip and a method of using the same for forming a taped leadframe package. In a top view shown in FIG. 1 a, a strip of metal film isattached to tape (10). The attachment of the tape to the metal film canbe accomplished in a number of ways, including conventional laminationtechniques, or using an adhesive. Alternatively, a metal film can bescreen printed onto a disposable tape or film, including glass filmcarrier to achieve a thinner package. The metal film is then patternedto form an array of lead frames (20) with each metal feature as shown inFIG. 1 a. As shown in FIGS. 1 b and 1 c, each lead frame comprises aplurality of metal features including chip pad (23) and a set of leadcontacts (25) surrounding the chip pad. The areas comprising features ofthe chip pad (23) and lead contacts (25) is collectively referred to asa chip site. A stiffener (30) optionally may be disposed on the lowersurface of the tape to provide additional mechanical stability duringprocessing.

The tape (10) comprises a plastic material, such as POLYIMIDE, MYLAR,KAPTON, or Fr-4, and may vary in thickness according to the application.The metal film, preferably copper or a copper alloy, may have athickness between about 1 to 4 mils, but may also have a thickness lessthan 1 mil. The metal film can be made as thin as possible, such as byscreening, as long as the metal is bondable. It is also preferred thatthe metal film is pre-plated, prior to mounting it onto the tape, with awire-bondable and solderable composition comprising Ni—Pd—Au-strike.

One approach to patterning can be stamping the pattern into the metal.Other approaches may include chemical or electrochemical milling andelectrical discharge machining. Photolithographic etching is preferred.The etching of the metal is performed until reaching the tape surface.Furthermore, the etching removes all the metal in between the features,and in between the lead frames because, the remaining metal features areheld in position by the underlying tape. Spaces devoid of metal betweenthe lead frames are referred to as “streets” (15) as shown in FIGS. 1 a,1 h, and 1 j.

The tape shown in FIG. 1 a, serving also as a carrier, advances to thenext process step where chips are mounted onto the chip pads of the leadframes. A flex tape along with a single-sided metal film can easilyaccommodate the conventional reel-to-reel assembly lines. At the nextassembly line station, then, chips (40) as shown in FIG. 1 d, aremounted onto the chip pads. FIG. 1 e shows a chip site where chip (40)is back-bonded, onto chip pad (23). The back bonding may be accomplishedusing epoxy (47) and through the use of solders or other eutectic metalsin paste or film form. After the epoxy cures, chip pad contacts (45) andlead contacts (25) are electrically connected by wires (50) usingwire-bonding techniques, as shown in FIG. 1 g. Because the lead framesformed according to the present invention have a continuous tapebacking, contacts (25) are firmly seated and held down on a flatsurface, thereby yielding excellent bonds, which improves thereliability of the end product.

As shown in FIG. 1 h, after the chips and the corresponding electroniccontacts are connected to one another, all the components on the frontside of the metal film and tape are covered with an encapsulant moldingmaterial (60), such as a resin. Encapsulant (60) is formed over themetal film and all exposed surfaces, including the lead frames and theirassociated wires (50), chips (40), contacts (125) and over the streetregions (15) of the tape. With the disclosed method, the presence of thetape prevents the commonly encountered problem of mold flashing to thefootprint on the underside of the package.

FIG. 1 i shows that the tape (10) and optional stiffener (30) are thenremoved. The tape may be removed by simply peeling it off or bydissolving it in a chemical solution. The resultant structure is anarray, or matrix, of lead frame packages formed into a block. The blockis then singulated at the street portions (15) into a plurality ofelectronic packages (80) as shown in FIG. 1 j. Singulation can beaccomplished in a number of ways, including saw slicing shown in FIG. 1j, water-jet-cut, laser-cut, or a combination thereof, or othertechniques that are especially suitable for cutting plastics. The bottomsurface of each singulated package, shown in FIG. 1 k, is clean andready for further processing. The pre-plated contacts can be connectedto the next level of packaging. If desired, the already clean contactscan be further smoothed out or flash soldered for improved connections.

A block of lead frames can be of any size commensurate with the desiredproductivity on the manufacturing line. A top view of such a block isshown in FIG. 1 l. A portion of the block is shown in FIG. 1 m, while achip site is shown in FIG. 1 n. A summary of the process steps forforming a taped lead frame package of the invention is summarized inFIG. 10. Preferred steps include forming a lead frame chip site (90),followed by chip, or die, attach. The attachment is performed throughthe use of solder, other eutectic metals or by an epoxy which then iscured and dried at step (92). Next, chip terminals are wire-bonded tolead contacts in step (93), which is followed by encapsulation in amolding material (94). Next, tape is removed at step (95) after which,the molded block is singulated (96) to form the individual packages.

In another embodiment shown in FIGS. 2 a-2 r, a method of forming ataped lead frame for a flip-chip and a method of using the same forforming flip chip electronic packages are disclosed. Following processsteps similar to those of the previous embodiment, a strip of metal filmis attached to tape (100), as shown in FIG. 2 a. The metal film is thenpatterned to form an array of lead frames with metal features formingchip sites (120), better seen in FIG. 2 b. Features in this embodimentcomprise a set of lead contacts (125). The contacts have short leadswith ends (123), which extend inward towards the center of the leadframe. The ends of the short leads provide areas to join the bumps on aflip-chip, as shown at a later step. A cross-sectional view of the chipsite in FIG. 2 b is shown in FIG. 1 c.

Tape carrier (100) is preferably POLYIMIDE, MYLAR, KAPTON, or Fr-4.Alternatively, an equivalent carrier that can be removed or disposedlike glass-film or shiny plastic film, or similar, is used. The metalfilm, preferably copper, has a thickness between about 1 to 4 mils, andcan have a thickness less than 1 mil. The metal film can be made as thinas possible as long as the metal is bondable. It is also preferred thatthe metal film is pre-plated, prior to mounting it onto the tape.

The patterning is accomplished by using photolithographic etching. Theetching removes all metal until reaching the underlying tape, except forthe features in the lead frames forming the chip sites. The lead framesare thus separated by streets (115) shown in FIGS. 2 a, 2 h, and 2 j.The features of the lead frame are held in position by the underlyingtape with connections neither between the lead frames nor between thefeatures within a lead frame chip site. The absence of metal in thestreets assures no sawing into any metal during the singulation process,as already disclosed in the previous embodiment. As in the previousembodiment, one can use a similar stiffener (130) behind the tape, asshown in FIG. 2 c.

At the next step, chip (140) shown in FIG. 2 d with solder bumps (145)is flipped over so that bumps (145) are placed over features (123) asshown in FIGS. 2 e and 2 f. A solder reflow operation is then performedand the solder bumps collapse somewhat forming shortened solderconnections (150) as seen in FIG. 2 g. The presence of the tape alongwith the stiffener provides the needed stability to form good flip-chipbonds as depicted in FIG. 2 g.

After the flip-chips are attached and electrically connected to the leadframes, the lead frames on the tape are encapsulated in a moldingmaterial as shown in FIG. 2 h. Encapsulant (160) is formed all aroundthe chips as well as over all features in each lead frame chip site.

Once the encapsulant is cured and dried, the tape and optional stiffenerare removed. The removal of the tape can be accomplished in any numberof ways, as mentioned earlier. The resultant structure is an array, ormatrix, of lead frame packages formed into a block, as shown in FIG. 2i. Because the lead frames in the block are electrically isolated fromeach other, block, or strip testing may be performed at this stage,prior to singulation. The block is then singulated at street portions(115) into a plurality of electronic packages (180) as shown in FIG. 2j. The bottom surface of each singulated package, shown in FIG. 2 k, isclean and ready for further processing. The pre-plated contacts can beconnected to the next level of packaging. If desired, the already cleancontacts can be further smoothened out or flash soldered for improvedconnections.

FIGS. 2 l, 2 m and 2 n show different types of electronic packages thatcan be obtained using the disclosed method of forming taped lead framepackages. FIG. 2 l is an enlarged view of FIG. 2 k, where cuts under thecontact leads, called “lips” (127) can be better seen. The lips areformed by half-etching the extension of contact leads (125) from thebottom surface after the tape has been removed, and prior toencapsulation. This method prevents the lead/contact extension frombeing exposed to the bumped bond-pad location during encapsulation.Also, the lips capture and lock onto the molding material, therebymaking it difficult for the molding material to separate from the matingsurfaces. As a further locking mechanism, the vertical walls of thefeatures can be patterned with reentrant features which will then holdonto the molding material, and prevent delamination at themetal-encapsulant interfaces. In a further embodiment, In FIG. 2 m,dummy bumps (155) and pad (145) are used to provide a thermal path forthermal enhancement. Also, contacts (125) can be shortened as shown inFIG. 2 n to provide a near chip size package.

FIG. 2 o shows a top view of a block of taped lead frames forflip-chips. A portion of the block is shown in FIG. 2 p, while a chipsite is shown in FIG. 2 q. A summary of the process steps for formingsuch packages is presented in FIG. 2 r. Preferred steps comprise forminglead frame chip sites (190), followed by flip-chip placement and solderreflow (192). Next, encapsulation with a molding material is performed(194). Then, the tape backing, including the stiffener, if present, isremoved at step (196) after which, the molded block is singulated (198)to form the individual flip chip packages.

In the next embodiment shown in FIGS. 3 a-3 q, a method of forming ataped land grid array package and a method of using the same for formingland grid array electronic packages are disclosed. The process steps forthe land grid array package follow very closely the process stepsdisclosed for the flip chip package. This embodiment leads to formingactual chip size packages with smaller footprints and more integratedfeatures.

Namely, a strip of metal film is attached to tape (200) as in previousembodiments, and as shown in FIG. 3 a. The metal film is then patternedto form an array of lead frames with features forming chip sites (220),better seen in FIG. 3 b. Features in this embodiment comprise a set ofround lead contacts (225). A cross-sectional view of the chip site inFIG. 3 b is shown in FIG. 3 c. FIG. 3 c also shows optional stiffener(230).

The patterning is accomplished by using photolithographic etching. Theetching removes all metal until reaching the underlying tape, except forthe features in the lead frames forming the chip sites (220). The leadframes are thus separated by streets (215), while the features of thelead frame are held in position by the underlying tape.

At the next step, integrated circuit chips are attached and electricallyconnected to the lead frames. Chip (240) shown in FIG. 3 d has a landgrid array of solder bumps (245). The bumps are formed at spacingscorresponding to the spacings between contacts (125) in each chip site(220). The chip is flipped over so that bumps (245) are placed overfeatures (225) as shown in FIG. 3 e. FIG. 3 e shows two such chip siteswith two solder bumped chips, but better seen in FIG. 3 f. Solder reflowoperation is performed causing the solder bumps to collapse somewhat andform shortened solder connections (250) as seen in FIG. 3 f.

After the flip-chips are attached and electrically connected to the leadframes, the lead frames on the tape are encapsulated in a moldingmaterial as shown in the same FIG. 3 f. Encapsulant (260) is formed allaround and under the chips. The presence of the tape prevents thecommonly encountered problem of mold flashing to the footprint on theunderside of the package.

Once the encapsulant is cured and dried, the tape and optional stiffenerare removed. The removal of the tape can be accomplished in any numberof ways, including simply peeling it off, or dissolving chemically. Theresultant structure is an array, or matrix, of lead frame packagesformed into a block, as shown in FIG. 3 g. The block is then singulatedat street portions (215) into a plurality of electronic packages (280)as shown in FIG. 3 h, without cutting into any metal.

An enlarged view of one of the packages is shown in FIG. 3 i. Thefootprint of the package is very close to the footprint of the chip,except for the thickness of molding material (260) on the sides of thepackage. Solder bumps on the chip line up directly with features (225)that connect to the next level of packaging. This is better seen on thebottom view of the package shown in FIG. 3 j. If desired, the alreadyclean contacts can be further smoothed out or flash soldered forimproved connections. Other examples of land grid array packages with a“lip” are shown in FIGS. 3 k-3 m. FIG. 3 k shows a package with 256lands while FIG. 3 l shows a similar package with 144 lands. The packagein FIG. 3 m has 36 lands.

Similar to FIGS. 1 l and 2 o, FIG. 3 n shows a top view of a block oftaped lead frames for flip-chips with land grid array of bumps. Aportion of the block is shown in FIG. 3 o, while a chip site is shown inFIG. 3 p. A summary of the process steps for forming a land grid arraypackage is summarized in FIG. 3 q. Preferred steps comprise formingtaped lead frame chip sites (300), followed by land grid array flip-chipplacement and solder reflow (301). Next, encapsulation with a moldingmaterial is performed (303). Then, the tape backing, including thestiffener, if present, is removed at step (305) after which, the moldedblock is singulated (307) to form the individual TLPF packages.

The invention enables the thickness of conventional lead frames toshrink significantly to result in thinner packages for improved heatdissipation and shorter geometries for improved electrical performance.It provides opportunities of mass production of extremely thin packages.

While the invention has been particularly shown and described withreference to particular embodiments, those skilled in the art willunderstand that various changes in form and details may be made withoutdeparting form the spirit and scope of the invention.

1. A taped lead frame comprising: a tape; and a lead frame formed from aplurality of individual metal features attached to the tape and arrangedin a footprint pattern for providing support and electrical connectionto an integrated circuit chip, each metal feature electrically isolatedfrom the other metal features in the pattern.
 2. The taped lead frameaccording to claim 1, further comprising a wire-bondable and solderablecomposition pre-plated on either or both a first and second surface ofeach metal feature.
 3. The taped lead frame according to claim 2,wherein the wire-bondable and solderable composition is Ni—Pd—Au-strike.4. The taped lead frame according to claim 1, wherein the tape and metalfeatures are attached by an adhesive on the tape.
 5. The taped leadframe according to claim 1, wherein the tape and metal features areattached by lamination.
 6. The taped lead frame according to claim 1,wherein the metal features are screen printed onto a disposable tape,film, including glass film, or other carrier equivalents.
 7. The tapedlead frame according to claim 1, further comprising a stiffener disposedon a lower surface of the tape.
 8. The taped lead frame according toclaim 1, wherein the metal features have a thickness of about 1-4 mils.9. The taped lead frame according to claim 1, wherein the metal featureshave a thickness of less than about 1 mil.
 10. The taped lead frameaccording to claim 1, wherein the tape comprises a plastic material. 11.The taped lead frame according to claim 10, wherein the tape comprisesPOLYIMIDE, MYLAR, KAPTON, or Fr-4.
 12. The taped lead frame according toclaim 1, wherein the metal features in the footprint pattern include adie pad for supporting an integrated circuit chip and lead contacts forelectrically connecting the lead frame to the chip.
 13. The taped leadframe according to claim 12, wherein the lead frame provides support andconnection for a wire bonded chip.
 14. The taped lead frame according toclaim 1, wherein the metal features in the footprint pattern includelead contacts for supporting an integrated circuit chip and forelectrically connecting the lead frame to the chip.
 15. The taped leadframe according to claim 14, wherein the lead frame provides support andconnection for a flip-chip or a land grid array chip.
 16. The taped leadframe according to claim 1, wherein the tape is removable from the metalfeatures by peeling, dissolving or back patterning.
 17. An array oftaped lead frames for mass producing electronic packages comprising: atape; and a plurality of individual metal lead frames attached to thetape, each lead frame separated from adjacent lead frames by streetregions on the tape, each lead frame comprising a plurality ofindividual metal features arranged in a footprint pattern, each metalfeature electrically isolated from other metal features in a pattern andno metal feature extending into a street region.
 18. The array of tapedlead frames according to claim 17, further comprising a wire-bondableand solderable composition pre-plated on either or both a first andsecond surface of each metal feature.
 19. The array of taped lead framesaccording to claim 17, wherein the wire-bondable and solderablecomposition is Ni—Pd—Au-strike.
 20. The array of taped lead framesaccording to claim 17, wherein the tape and metal features are attachedby an adhesive on the tape.
 21. The array of taped lead frames accordingto claim 17, wherein the tape and metal features are attached bylamination.
 22. The array of taped lead frames according to claim 17,further comprising a stiffener disposed on a lower surface of the tape.23. The array of taped lead frames according to claim 17, wherein themetal features have a thickness of about 1-4 mils.
 24. The array oftaped lead frames according to claim 17, wherein the metal features havea thickness of less than about 1 mil.
 25. The array of taped lead framesaccording to claim 17, wherein the tape comprises a plastic material.26. The array of taped lead frames according to claim 25, wherein thetape comprises POLYIMIDE, MYLAR, KAPTON, or Fr-4.
 27. The array of tapedlead frames according to claim 17, wherein the metal features in thefootprint pattern include a die pad for supporting an integrated circuitchip and lead contacts for electrically connecting the lead frame to thechip.
 28. The array of tape lead frames according to claim 27, whereinthe lead frame provides support and connection for a wire bonded chip.29. The array of taped lead frames according to claim 17, wherein themetal features in the footprint pattern include lead contacts forsupporting an integrated circuit chip and for electrically connectingthe lead frame to the chip.
 30. The array of taped lead frames accordingto claim 29, wherein the lead frame provides support and connection fora flip-chip or a land grid array chip.
 31. The array of taped leadframes according to claim 17, wherein the tape is removable from themetal features by peeling, dissolving or back patterning.
 32. A methodof forming a lead frame comprising the steps of: providing a metal film;attaching a tape to the film; and patterning the film to leave a metallead frame on the tape, the lead frame comprising a plurality of metalfeatures arranged in a footprint pattern, each metal featureelectrically isolated from the other metal features in the pattern. 33.The method according to claim 32, further comprising the step ofpre-plating an upper or lower surface of the film or both surfaces witha wire-bondable and solderable composition.
 34. The method according toclaim 33, wherein the composition is Ni—Pd—Au-strike.
 35. The methodaccording to claim 32, wherein the tape and film are attached by anadhesive on the tape.
 36. The method according to claim 32, wherein thetape and the film are attached by lamination.
 37. The method accordingto claim 32, wherein the metal features are screen printed onto adisposable tape, film, including glass film, or other carrierequivalents.
 38. The method according to claim 32, further comprisingthe steps of attaching a stiffener to the tape; and removing thestiffener before removing the tape.
 39. The method according to claim32, wherein the film has a thickness of about 1-4 mils.
 40. The methodaccording to claim 32, wherein the film has a thickness of less thanabout 1 mil.
 41. The method according to claim 32, wherein the tapecomprises a plastic.
 42. The method according to claim 41, wherein thetape comprises POLYIMIDE, MYLAR, KAPTON, or Fr-4.
 43. The methodaccording to claim 32, wherein the metal features in the footprintpattern include a die pad for supporting the integrated circuit chip andlead contacts for electrically connecting the lead frame to the chip.44. The method according to claim 43, wherein the lead frame providessupport and connection for a wire-bonded chip.
 45. The method accordingto claim 32, wherein the metal features in each footprint patterninclude lead contacts for supporting an integrated circuit chip and forelectrically connecting the lead frame to the chip.
 46. The methodaccording to claim 45, wherein the lead frame provides support andelectrical connection for a flip-chip or land grid array chip.
 47. Amethod of forming an electronic package comprising the steps of:providing a metal film; attaching a tape to the film; patterning thefilm to leave a metal lead frame on the tape, the lead frame comprisinga plurality of metal features arranged in a footprint pattern, eachmetal feature electrically isolated from the other metal features in thepattern; attaching and electrically connecting an integrated circuitchip to the metal features of the lead frame; encapsulating the leadframe on the tape; removing the tape; and singulating the encapsulantwithout singulating any metal feature to form an electronic packages.48. The method according to claim 47, further comprising the step ofpre-plating an upper or lower surface of the film or both surfaces witha wire-bondable and solderable composition.
 49. The method according toclaim 48, wherein the composition is Ni—Pd—Au-strike.
 50. The methodaccording to claim 47, wherein the tape and film are attached by anadhesive on the tape.
 51. The method according to claim 47, wherein thetape and the film are attached by lamination.
 52. The method accordingto claim 47, wherein the metal features are screen printed onto adisposable tape, film, including glass film, or other carrierequivalents.
 53. The method according to claim 47, further comprisingthe steps of attaching a stiffener to the tape; and removing thestiffener before removing the tape.
 54. The method according to claim47, wherein the film has a thickness of about 1-4 mils.
 55. The methodaccording to claim 47, wherein the film has a thickness of less thanabout 1 mil.
 56. The method according to claim 47, wherein the tapecomprises a plastic.
 57. The method according to claim 53, wherein thetape comprises POLYIMIDE, MYLAR, KAPTON, or Fr-4.
 58. The methodaccording to claim 47, wherein the metal features in the footprintpattern include a die pad for supporting the integrated circuit chip andlead contacts for electrically connecting the lead frame to the chip.59. The method according to claim 58, wherein the integrated circuitchip is attached to the die pad by epoxy, solder, or other eutecticmetals.
 60. The method according to claim 55, wherein the lead frameprovides support and connection for a wire-bonded chip.
 61. The methodaccording to claim 47, wherein the metal features in each footprintpattern include lead contacts for supporting an integrated circuit chipand for electrically connecting the lead frame to the chip.
 62. Themethod according to claim 57, wherein the lead frame provides supportand electrical connection for a flip-chip or land grid array chip. 63.The method according to claim 47, wherein the tape is removed bypeeling, dissolving or back patterning the tape away from the metalfeatures and the encapsulant to expose the footprint pattern of the leadframe.
 64. The method according to claim 47, wherein the encapsulatingstep includes applying an encapsulant material over the lead frame in acontrolled manner to flow around the metal features and up to the tapesurface without creating any mold flash.
 65. The method according toclaim 47, wherein the singulating step comprises sawing, laser cutting,water jet cutting or a combination thereof.
 66. The method according toclaim 47, further comprising performing strip testing of the packageprior to singulating the encapsulant.
 67. A method of forming aplurality of electronic packages comprising the steps of: providing ametal film; attaching a tape to the film; patterning the film to leave aplurality of individual metal lead frames on the tape, each lead frameseparated from adjacent lead frames by street regions on the tape, eachlead frame comprising a plurality of metal features arranged in afootprint pattern and electrically isolated from one another, and nometal features extending into the street regions on the tape; attachingand electrically connecting an integrated circuit chip to the metalfeatures of each lead frame; encapsulating the lead frames and thestreet regions on the tape; removing the tape; and singulating theencapsulant in the street regions to form individual electronicpackages.
 68. The method according to claim 67, wherein the metal filmhas first and surfaces and either or both said surfaces are pre-platedwith a wire-bondable and solderable composition.
 69. The methodaccording to claim 64, wherein the composition is Ni—Pd—Au-strike. 70.The method according to claim 67, wherein the tape and film are attachedby an adhesive on the tape.
 71. The method according to claim 67,wherein the tape and the film are attached by lamination.
 72. The methodaccording to claim 67, wherein the metal features are screen printedonto a disposable tape, film, including glass film, or other carrierequivalents.
 73. The method according to claim 67, further comprisingthe steps of attaching a stiffener to the tape when the tape is attachedto the film; and removing the stiffener prior to removing the tape. 74.The method according to claim 67, wherein the film has a thickness ofabout 1-4 mils.
 75. The method according to claim 67, wherein the filmhas a thickness of less than about 1 mil.
 76. The method according toclaim 67, wherein the tape is composed of POLYIMIDE, MYLAR, KAPTON, orFr-4.
 77. The method according to claim 67, wherein the metal featuresin each footprint pattern include a die pad for supporting theintegrated circuit chip and lead contacts for electrically connectingthe lead frame to the chip.
 78. The method according to claim 75,wherein the lead frames provide support and connection for a wire-bondedchip.
 79. The method according to claim 67, wherein the metal featuresin each footprint pattern include lead contacts for supporting anintegrated circuit chip and for electrically connecting the lead frameto the chip.
 80. The method according to claim 79, wherein theintegrated circuit chip is attached to the die pad by epoxy, solder, orother eutectic metals.
 81. The method according to claim 79, wherein thelead frame provides support and electrical connection for a flip-chip orland grid array chip.
 82. The method according to claim 67, wherein theplurality of lead frames are formed in an array on the tape.
 83. Themethod according to claim 67, wherein the tape is removed by peeling,dissolving or back patterning the tape away from the metal features andthe encapsulant to expose the footprint pattern of the lead frame. 84.The method according to claim 67, wherein the encapsulating stepincludes applying an encapsulant material over the lead frame and in thestreet regions in a controlled manner to flow around the metal featuresand up to the tape surface without creating any mold flash.
 85. Themethod according to claim 67, wherein the singulating step comprisessawing, laser cutting, water jet cutting or a combination thereof. 86.The method according to claim 67, further comprising performing striptesting of the package prior to singulating the encapsulant.